The present invention relates to a method and/or architecture for implementing zero delay buffers (ZDBs) generally and, more particularly, to a method and/or architecture for implementing ZDB technology with multiple output clock instantiations of a reference clock input with a predicted delay.
Zero delay buffer (ZDB) technology implements multiple output clock instantiations of a reference clock input (i.e., the output clock signals are derived from the reference clock signal) with delay on the output clock instantiations. ZDB circuits are typically implemented in the context of a phase locked loop (PLL) circuit or circuits. The delay mechanism is implemented as internal feedback and can be positive (the traditional approach) or negative (a relatively new concept).
The frequency timing relationship between input and output clocking rates typically maintains a 1:1 frequency ratio over a substantial input reference frequency range and, as such, the PLL circuitry is designed so that a wide variation in the input reference frequency range can be accommodated. While the majority of ZDB technology is implemented with the 1:1 relationship, other ratios (i.e., 2:1, 4:1, etc.) are implemented depending on output divisor structures. ZDB technology has a proportionally high input reference frequency when compared to standard frequency synthesizer topologies. ZDB technology has a high update rate and a low jitter output response.
Referring to FIG. 1, a block diagram illustrating a conventional ZDB circuit 10 is shown. The ZDB circuit 10 includes a PLL 12 and a number of output buffers 14a-14n. The PLL 12 includes a phase detector 20, a loop filter 22, and a voltage controlled oscillator (VCO) 24 that are serially connected. The PLL 12 receives a reference input clock signal REF_IN at a first input to the phase detector 20 and the output buffers 14a-14n present clock signals CLKa-CLKn. One of the clock signals (i.e., CLKa) is also implemented as a feedback clock signal FEEDBACK to the PLL 12 at a second input to the phase detector 20.
In another implementation (not shown), the ZDB 10 includes a frequency divider circuit at the reference clock signal input to the phase detector 20. Similarly, the path of the signal FEEDBACK can include a frequency divider circuit that divides the signal FEEDBACK by the same or by a different value than the value that the signal REF_IN is divided by.
The VCO 24 frequency synthesizes an output clock signal that is presented to the buffers 14a-14n in response to the reference input frequency REF_IN and the divisor value (when implemented) in the feedback path. Under normal synthesizer operation, output frequency accuracy is a concern. However, for ZDB devices such as the circuit 10 the minute changes in the VCO 24 output frequency causes a slight phase difference between the signal REF_IN and the output clock signals CLKa-CLKn. The phase variation in the sampled time domain appears as a positive or negative delay depending if the VCO 24 output signal is slightly lagging or leading, respectively, the reference input REF_IN.
Since the ZDB 10 replicates the reference clock frequency input (i.e., REF_IN), multiple instantiations of the input clock are generated n times (i.e., the output clock signals CLKa-CLKn) to be distributed throughout the target system where the circuit 10 is implemented. That is, while the buffer 14a (i.e., the signal CLKa) is part of a closed-loop PLL system, the remaining output buffers 14b-14n (i.e., the signals CLKb-CLKn) function in an open-loop mode. The open-loop implementation of ZDB circuits is especially suited to clocking amplification. Clocking amplification is normally a limiting function in a digital system. Open-loop circuits are susceptible to independent propagation characteristics that are manifested under manufacturing specifications commonly defined as propagation delay. Propagation delay is characterized by the manufacturing product data sheet parameters that include minimum, typical, and maximum propagation delay specifications.
The open-loop nature of the circuit 10 indicates that an output response is susceptible to the variations in parametric elements such as temperature, supply voltage, loading effect propagation characteristics, etc. that are common to systems where ZDB circuits are implemented. To mitigate the impact of the parametric element variations, feedback is introduced. The introduction of feedback appears to be a trivial concept at first, especially in a 1:1 frequency relationship. However, feedback has a profound effect on the ZDB circuit. When feedback is introduced, the ZDB circuit becomes a closed-loop system. External factors such as temperature, supply voltage and output loading variations become part of the error term in the feedback path that is compensated or cancelled in the ZDB circuit. Feedback mitigates external effects and ensures high predictability and accuracy in the production of the output signal edges in the ZDB circuit.
Another important benefit of feedback is that the introduction of delay in a traditional open-loop system can be forced to a specific value in a closed-loop system. The fixed delay value is implemented via the feedback path forcing the VCO to compensate by proportionally speeding up (or slowing down) the edge rate of the VCO output signal, and thus forcing the phase detector inputs back into compliance. In a locked system, feedback compensates for inherent delay, and hence provides a true zerodelay path through the ZDB circuit.
Zero delay is defined as the edge alignment of the reference clock signal REF_IN edge input to the feedback buffered edge output (i.e., edge of the signals CLKa-CLKn). Some applications of ZDB type circuits require a known positive delay between reference and buffered output clock signals. Positive delay is generated via loading the non-feedback output buffer circuits. Negative delay can be generated via loading the feedback path (i.e., the signal FEEDBACK) with added capacitance. Delaying the signal FEEDBACK through capacitive loading forces the VCO 24 to speed up proportionally to compensate for the inherent delay in the feedback path placing the VCO 24 output clock signal edge prior to the input clock signal edge (hence negative delay).
The circuit 10 is implemented with one closed-loop path (i.e., the signal FEEDBACK via only the signal CLKa to the phase detector 20). The remaining output signals CLKb-CLKn operate in lock-step, but are not part of the closed loop system. As such, the output signals CLKb-CLKn are subject to parametric element variations impacting the overall response of each individual buffer 14b-14n. Thus, what may appear as closed-loop configurations for nxe2x88x921 outputs, are really open-loop outputs driven by a common source. This indicates a difference in the delay of each of the signals CLKa-CLKn relative to the signal REF_IN.
It would be desirable to have a ZDB circuit that (i) minimizes the difference in delay between all output clock signals, (ii) is implemented in a minimal die area, (iii) is programmable for a variety of feedback selection mechanisms, (iv) has dual-modulus capability, and/or (v) may be configured as a synchronous clocking tree.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to a first control signal. The first control signal may be configured to minimize a difference in delay between the plurality of output clock signals.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing zero delay buffer (ZDB) technology with multiple output clock instantiations of a reference clock input with a predicted delay that may (i) significantly enhance product robustness, (ii) implement multiplexed feedback, (iii) implement multiplexed divisor banking, (iv) minimize the difference in delay between all output clock signals, (v) be implemented in a minimal die area, (vi) be programmable for a variety of fixed or real-time feedback selection mechanisms or schemes (e.g., round-robin, binary weighted, etc.), (vii) include compensation for the delay in the feedback selection, (viii) have dual-modulus capability, (vi) approximate a completely closed loop system with a single PLL, (ix) have reduced cost when compared to multiple PLL ZDB implementations, (x) optimize the system response, (xi) implement fractional frequency synthesis, (xii) mitigate variations in temperature, supply voltage, supply ground, and/or output loading effects, and/or (xiii) be configured as a synchronous clocking tree.